UPD784020 Datasheet, PDF (46/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
9.3 CONTEXT SWITCHING
When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank
is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same
time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register
bank.
The branch address must be within the range of 0 to FFFFH.
Fig. 9-1 Context Switching Caused by an Interrupt Request
0000B
7 Transfer
PC19-16
PC15-0
2 Save
(Bits 8 to 11 of
temporary register)
6 Exchange
5 Save
Temporary register
1 Save
PSW
Register bank n (n = 0-7)
Register bank (0-7)
A
X
B
C
R5
R4
R7
R6
V
VP
U
UP
3 Switching between register banks
(RBS0-RBS2 ← n)
T
W
D
H
E
L
4
RSS ← 0
IE ← 0
9.4 MACRO SERVICE
The macro service function enables data transfer between memory and special function registers (SFRs) without
requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same
transfer cycle to directly transfer data without having to perform data fetch.
Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is
possible.
Fig. 9-2 Macro Service
CPU
Memory
Read
Write
Macro service
controller
Write
Read
SFR
Internal bus
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