UPD784020 Datasheet, PDF (51/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
10.3 PROGRAMMABLE WAIT
When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory
space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even
when memory devices having different access times are connected.
In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer
address decode time. (This function is set for the entire space.)
10.4 PSEUDO-STATIC RAM REFRESH FUNCTION
Refresh is performed as follows:
• Pulse refresh
: A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular
intervals. When the memory space is divided into eight, and a specified area
is being accessed, refresh pulses can also be output on the REFRQ pin as the
memory is being accessed. This can prevent the refresh cycle from suspending
normal memory access.
• Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the
contents of pseudo-static RAM.
10.5 BUS HOLD FUNCTION
A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus
hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus
cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance
state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master.
While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.
51