UPD784020 Datasheet, PDF (69/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
SERIAL OPERATION (IOE1, IOE2)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Serial clock cycle time
tCYSK1 Input
VDD = +5.0 V ±10 %
250
ns
(SCK1, SCK2)
500
ns
Output Internal clock divided by 16
T
ns
Serial clock low-level width
tWSKL1 Input
VDD = +5.0 V ±10 %
85
ns
(SCK1, SCK2)
210
ns
Output Internal clock divided by 16
0.5T – 40
ns
Serial clock high-level width tWSKH1 Input VDD = +5.0 V ±10 %
85
ns
(SCK1, SCK2)
210
ns
Output Internal clock divided by 16
0.5T – 40
ns
SI1, SI2 setup time
tSSSK1
40
ns
(referred to SCK1, SCK2•)
SI1, SI2 hold time
tHSSK1
40
ns
(referred to SCK1, SCK2•)
SO1, SO2 output delay time tDSOSK
0
50
ns
(referred to SCK1, SCK2Ø)
SO1, SO2 output hold time
tHSOSK During data transfer
0.5TCYSK1 – 40
ns
(referred to SCK1, SCK2•)
Remarks 1. The values listed in the above table are obtained when CL = 100 pF.
2. T: Serial clock frequency specified using software. The minimum value is 16/fXX.
SERIAL OPERATION (UART, UART2)
Parameter
ASCK clock input cycle time
Symbol
Conditions
tCYASK VDD = +5.0 V ±10 %
ASCK clock low-level width tWASKL VDD = +5.0 V ±10 %
ASCK clock high-level width tWASKH VDD = +5.0 V ±10 %
Min.
Max.
Unit
125
ns
250
ns
52.5
ns
85
ns
52.5
ns
85
ns
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