UPD784020 Datasheet, PDF (13/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
6.2 NON-PORT PINS (1/2)
Pin
TO0-TO3
CI
RXD
RXD2
TXD
TXD2
ASCK
ASCK2
SB0
SI0
SI1
SI2
SO0
SO1
SO2
SCK0
SCK1
SCK2
NMI
INTP0
I/O
Output
Input
Input
Output
Input
I/O
Input
Output
I/O
Input
Dual-function
P34-P37
P23/INTP2
P30/SI1
P13/SI2
P31/SO1
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P33/SO0
P27
P30/RXD
P13/RXD2
P33/SB0
P31/TXD
P14/TXD2
P32
P25/INTP4/ASCK
P12/ASCK2
P20
P21
INTP1
P22
INTP2
P23/CI
INTP3
P24
INTP4
INTP5
AD0-AD7
A8-A15
A16-A19
RD
WR
WAIT
REFRQ
HLDRQ
HLDAK
ASTB
I/O
Output
Output
Output
Output
Input
Output
Input
Output
Output
P25/ASCK/SCK1
P26
—
—
P60-P63
—
—
P66/HLDRQ
P67/HLDAK
P66/WAIT
P67/REFRQ
—
Function
Timer output
Input of a count clock for timer/counter 2
Serial data input (UART0)
Serial data input (UART2)
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data I/O (SBI)
Serial data input (3-wire serial I/O0)
Serial data input (3-wire serial I/O1)
Serial data input (3-wire serial I/O2)
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock I/O (3-wire serial I/O0, SBI)
Serial clock I/O (3-wire serial I/O1)
Serial clock I/O (3-wire serial I/O2)
External interrupt request
—
Ý Input of a count clock for timer/counter 1
Ý Capture/trigger signal for CR11 or CR12
Ý Input of a count clock for timer/counter 2
Ý Capture/trigger signal for CR22
Ý Input of a count clock for timer/counter 2
Ý Capture/trigger signal for CR21
Ý Input of a count clock for timer/counter 0
Ý Capture/trigger signal for CR02
—
Input of a conversion start trigger for A/D converter
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address bus during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for
connecting external memory)
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