UPD703111A Datasheet, PDF (570/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 10 SERIAL INTERFACE FUNCTION
(15) Enabling/disabling transfer wait
In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), starting transfer can
be delayed by one clock for each time 1-bit data transfer is started, depending on the setting (1) of the
CSWEn bit of the CSIM3n register (CSWEn bit = 1 (transfer wait inserted)). The CSWEn bit is valid only in
the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register), setting the
CSWEn bit to 1 is prohibited (even if set, transfer wait is not inserted).
Figure 10-34. Enabling/Disabling Transfer Wait
SCKn (output)
(a) CSITn bit = 0, CSWEn bit = 1, CKPn and DAPn bits = 00,
CCLn3 to CCLn0 bits = 1000 (transfer data length: 8 bits)
Wait
SIn (input)
DI7
DI6
DI5
DI1
DI0
DI7
SOn (output)
DO7
DO6
DO5
DO1
DO0
DO7
(b) CSITn bit = 1, CSWEn bit = 1, CKPn and DAPn bits = 00,
CCLn3 to CCLn0 bits = 1000 (transfer data length: 8 bits)
Delay Wait
SCKn (output)
SIn (input)
DI7
DI6
DI5
DI1
DI0
DI7
SOn (output)
DO7
DO6
DO5
DO1
DO0
DO7
INTCSI3n interrupt
Remark n = 0, 1
Delay
570
User’s Manual U16031EJ4V1UD