UPD703111A Datasheet, PDF (396/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 8 CLOCK GENERATION FUNCTION
(2) Release of IDLE mode
The IDLE mode is released by a non-maskable interrupt request signal, an unmasked external maskable
interrupt request signal (INTPn)^Note, an unmasked internal maskable interrupt request signal of a peripheral
function that can operate in the IDLE mode (INTRSUM), and RESET pin input (n = 10, 11, 21 to 25, 50 to 52,
65 to 67, D0 to D15, L0, or L1).
Note When level detection is set, the IDLE mode cannot be released.
(a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal
IDLE mode can be released by an interrupt request signal only when it has been set with the INTM and
NMIM bits of the PSC register cleared to 0.
IDLE mode is released by a non-maskable interrupt request signal, an unmasked external maskable
interrupt request signal (INTPn), or an unmasked internal maskable interrupt request signal of a
peripheral function that can operate in the IDLE mode (INTRSUM) regardless of the priority (n = 10, 11,
21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). The operation after release is as follows.
Caution When the INTM bit of the PSC register = 1, the IDLE mode cannot be released by the
unmasked maskable interrupt request signal.
Table 8-7. Operation After IDLE Mode Is Released by Interrupt Request Signal
Release Source
Non-maskable interrupt request
signal
Unmasked maskable interrupt
request signal
Enable Interrupt (EI) Status
Branch to handler address
Branch to handler address or
execute next instruction
Disable Interrupt (DI) Status
Execute next instruction
However, if the system is set to IDLE mode during an interrupt servicing routine, operation will differ as
follows.
(i) If an interrupt request signal is generated with a lower priority than that of the maskable interrupt
request signal that is currently being serviced, IDLE mode is released, but the newly generated
interrupt request signal is not acknowledged. The new interrupt request signal is held pending.
(ii) If an interrupt request signal (including non-maskable interrupt request signals) is generated with a
higher priority than that of the maskable interrupt request signal that is currently being serviced, IDLE
mode is released and the newly generated interrupt request signal is acknowledged.
If the system is set to IDLE mode during an NMI servicing routine, IDLE mode is released, but the
interrupt is not acknowledged (interrupt is held pending).
Interrupt servicing that is started when IDLE mode is released by NMI pin input is handled in the same
way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt
handler address is unique). Therefore, when a program must be able to distinguish between these two
situations, a software status must be prepared in advance and that status must be set before setting the
PSMR register using a store instruction or a bit manipulation instruction. By checking for this status
during NMI interrupt servicing, an ordinary NMI can be distinguished from the processing that is started
when IDLE mode is released by NMI pin input.
(b) Release according to RESET pin input
This is the same as a normal reset operation.
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User’s Manual U16031EJ4V1UD