UPD703111A Datasheet, PDF (170/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 4 BUS CONTROL FUNCTION
4.10.2 Operation
(1) Read operation
The internal instruction RAM can be read by normal RAM access without having to be aware of the banks if
the read mode is selected by the IRAMM register.
Cautions 1. A bank in the write mode cannot be read.
2. The internal instruction RAM (in the read mode) is accessed using the ×1 internal
system clock (fCLK).
(2) Write operation
The internal instruction RAM can be written by normal RAM access without having to be aware of the banks if
the write mode is selected by the IRAMM register.
Cautions 1. A bank in the read mode cannot be written.
2. Internal instruction RAM bank 0 area is allocated to interrupt and exception tables.
Disable interrupts until writing an instruction code to bank 0 of the internal instruction
RAM is completed. Similarly, disable interrupts when bank 0 of the internal instruction
RAM is set in the write mode.
For disabling maskable interrupts, refer to interrupt mask registers 0 to 5 (IMR0 to IMR5)
(7.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5)). To disable the non-maskable
interrupt, set the NP bit of the PSW to 1 to disable multiple interrupts (see 3.2.2 (4)
Program status word (PSW)). For the NMI mask operation when reset is cleared, refer to
the NMI reset status register (NRS) (7.3.6 NMI reset status register (NRS)).
3. Since the internal instruction RAM (in the write mode) is accessed using BUSCLK
(internal instruction RAM (in the read mode) is accessed using internal system clock
(fCLK)), programmable waits, address setup waits, and idle states can be inserted for the
CS0 space.
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User’s Manual U16031EJ4V1UD