UPD703111A Datasheet, PDF (344/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
7
INTR2
0
INTF2
0
6
5
4
3
2
1
0
Address After reset
0
INTR25 INTR24 INTR23 INTR22 INTR21 NMIR0 FFFFFC24H
3FH
0
INTF25 INTF24 INTF23 INTF22 INTF21 NMIF0 FFFFFC04H
00H
Bit position
5 to 1
Bit name
INTF2n,
INTR2n
(n = 1 to 5)
Function
Specify the trigger mode of the INTP2n pin.
INTF2n INTR2n
Operation
0
0
Falling edge
0
1
Rising edge
1
0
Level detection (low-level detection)^{Notes 1, 2}
1
1
Both rising and falling edges
Notes 1.
2.
The level of the INTP2n pin is sampled each time the main clock (fX) is divided by four. When the
low level of this pin is detected, an interrupt request is latched as the P2IFn bit (n = 1 to 5).
Consequently, even when the CPU acknowledges the interrupt and the P2IFn bit of the interrupt
control register (P2ICn) is automatically cleared to 0, the P2IFn bit is immediately set to 1 and
interrupts occur consecutively. To avoid this status, make the INTP2n pin of the external device
inactive in the interrupt servicing routine, and forcibly clear the P2IFn bit to 0.
If a level-detected interrupt request (INTP2n) with a lower priority occurs while an interrupt is being
serviced and if this level-detected interrupt request (INTP2n) that has newly occurred becomes
inactive before the current interrupt has been serviced, the interrupt request of the new interrupt
(INTP2n) is held pending (n = 1 to 5). To not acknowledge the interrupt request of INTP2n, clear
the P2IFn bit of the interrupt control register.
Remark
For the bit 0 (NMIR0) of the INTR2 register and bit 0 (NMIF0) of the INTF2 register, see 7.2.4 (1)
External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge
specification register 2 (INTF2).
344
User’s Manual U16031EJ4V1UD