UPD703111A Datasheet, PDF (203/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
5.2.5 Page ROM access
Figure 5-5. Page ROM Access Timing (1/6)
(a) When read (without speculative read, 32-bit bus width, other than cache fill operation)
BUSCLK (output)
T0^{Note 1}
A0 to A25 (output)
BCYST (output)
CS0 to CS7 (output)
RD (output)
H
WR (output)
Note 2 (output)
D0 to D31 (input)
WAIT (input)
T1
T2
T0^{Note 1}
Off-page address
Data
T1
T2
T0^{Note 1}
Off-page address
Data
T1
T2
T0^{Note 1}
Off-page address
Data
T1
T2
T0^{Note 1}
Off-page address
Data
Notes 1. State (T0) inserted between bus cycles
2. UUBE, ULBE, LUBE, LLBE
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
User’s Manual U16031EJ4V1UD
203