UPD703111A Datasheet, PDF (236/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-11. SDRAM Access Timing (3/9)
(c) When read (16-bit bus width, cache fill operation, latency = 3)
BUSCLK (output)
Command
T0^{Note 1}
A1 to A10 (output)
A11 (output)
Bank address (output)
Note 2 (output)
BCYST (output)
CSn (output)
SDRAS (output) ^H
SDCAS (output)
WE (output) H
Note 3 (output)
D0 to D15 (I/O)
TREAD TREAD TREAD TREAD TREAD TREAD TREAD TREAD
TLATE
TLATE
TLATE
RD
RD
RD
RD
RD
RD
RD
RD
Col. (A) Col. (A+2) Col. (A+4) Col. (A+6) Col. (A+8) Col. (A+A) Col. (A+C) Col. (A+E)
Address Address Address Address Address Address Address Address
Address Address Address Address Address Address Address Address
Address Address Address Address Address Address Address Address
Undefined
Undefined
Undefined
Undefined
Data
Data
Data
Data
Data
Data
Data
Latency = 3
Latency = 3
Latency = 3
Latency = 3
Latency = 3
Latency = 3
Latency = 3
Latency = 3
Data
T0^{Note 1}
Notes 1.
2.
3.
State (T0) inserted between bus cycles
Addresses other than the bank address, A11, and A1 to A10.
UUDQM, ULDQM, LUDQM, LLDQM
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
3. Col.: Column address
236
User’s Manual U16031EJ4V1UD