UPD703111A Datasheet, PDF (158/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 4 BUS CONTROL FUNCTION
4.7.2 External wait function
When an extremely slow memory, I/O, or asynchronous system is connected, an arbitrary number of wait states
can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device.
Just as with programmable waits, accessing internal instruction RAM (in the read mode), internal data RAM, and
on-chip peripheral I/O areas cannot be controlled by external waits.
The external WAIT signal can be input asynchronously to BUSCLK and is sampled at the rising edge of BUSCLK
immediately after the T1 and TW states of a bus cycle. If the setup/hold time in the sampling timing is not satisfied,
the wait state may or may not be inserted in the next state.
4.7.3 Relationship between programmable wait and external wait
A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the
programmable wait and the wait cycle controlled by the WAIT pin.
Programmable wait
Wait by WAIT pin
Wait control
For example, if the timings of the programmable wait and the WAIT pin signal are as illustrated below, three wait
states will be inserted in the bus cycle.
Figure 4-6. Example of Wait Insertion
BUSCLK
WAIT pin
T1
TW
TW
TW
T2
Wait by WAIT pin
Programmable wait
Wait control
Remark The circle { indicates the sampling timing.
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User’s Manual U16031EJ4V1UD