UPD703111A Datasheet, PDF (279/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
6.5 Transfer Types
6.5.1 2-cycle transfer
In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle
(DMAC to destination).
In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the
second cycle, the destination address is output and writing is performed from the DMAC to the destination.
Cautions 1. An idle cycle of 1 to 2 clocks is always inserted between a read cycle and a write cycle.
2. See 6.15 (8) Restriction on 2-cycle DMA transfer for restrictions on 2-cycle DMA transfer.
Figure 6-8. Timing of 2-Cycle DMA Transfer (SRAM → External I/O) (1/2)
(a) Single transfer mode (0 waits, BMC register = 00H, level detection mode)
BUSCLK (output)
DMARQx (input)
DMAAKx (output)
BCYST (output)
CSm (output) of
SRAM area
CSn (output) of
external I/O area
RD (output)
WR (output)
Note 2 (output)
SDCKE (output) H
SDRAS (output) H
SDCAS (output) _H
D0 to D31 (I/O)
T1
T2
TI^{Note 1}
TI
T2
Data
Data
Notes 1. This idle state (TI) is independent of the BCC register setting.
2. UUBE/UUDQM, ULBE/ULDQM, LLBE/LLDQM, LUBE/LUDQM
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 0 to 7, m = 0 to 7 (n ≠ m)
x = 0 to 3
User’s Manual U16031EJ4V1UD
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