UPD703111A Datasheet, PDF (359/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
7.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850E/ME2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
7.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
15
11 10
54
0 31
27 26
23 22
16
0111
× × × × × 1 1 1 1 1 1 × × × × × × × × × × to × × × × × × 0
1111
×: Arbitrary
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is
recommended that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine:
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
control.
Figure 7-10 illustrates the processing of the exception trap.
User’s Manual U16031EJ4V1UD
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