UPD703111A Datasheet, PDF (176/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 4 BUS CONTROL FUNCTION
(2) SRAM (when read, with speculative read, no idle state inserted, BUSCLK = fCLK/2)
BUSCLK (output)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
BCYST (output)
CS0 to CS7 (output)
IORD^{Note 3}, RD (output)
Note 4 (output)
WR, IOWR (output)
D0 to D31 (input)
WAIT (input)
T1
T2
Data
T1
T2
TI^{Note 1}
TH
TH
Address
Undefined
Data
Notes 1.
2.
3.
4.
This idle state (TI) is independent of the BCC register setting.
State (T0) inserted between bus cycles
When the IOEN bit of the BCP register is set to 1.
UUBE, ULBE, LUBE, LLBE
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
176
User’s Manual U16031EJ4V1UD