UPD703111A Datasheet, PDF (311/974 Pages) NEC – 32-Bit Single-Chip Microcontroller

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
6.12 Forcible Termination
DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register, in addition to the forcible
interruption operation by means of NMI input (n = 0 to 3).
An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).
Figure 6-23. Example of Forcible Termination of DMA Transfer
(a) Block transfer through DMA channel 3 is started during single-step transfer through DMA channel 2
DSA2, DDA2, DBC2,
DADC2, DCHC2
DCHC2
(INIT2 bit = 1)
DMARQ2 (input)
Register set
E22 bit = 1
TC2 bit = 0
Register set
E22 bit → 0
TC2 bit = 0
DSA3, DDA3, DBC3,
DADC3, DCHC3
Register set
DMARQ3 (input)
E33 bit = 1
TC3 bit = 0
E33 bit → 0
TC3 bit → 1
CPU CPU CPU CPU DMA2 CPU DMA2 CPU DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU
DMA channel 3 terminal count
DMA channel 3 transfer start
Forcible termination of DMA channel 2 transfer
(b) When transfer is aborted during DMA channel 1 single-step transfer, and transfer under another
condition is executed
DSA1, DDA1, DBC1,
DADC1, DCHC1
DSA1, DDA1,
DBC1
DCHC1
(INIT1 bit = 1)
DADC1,
DCHC1
Register set
Register set
Register set Register set
DMARQ1 (input)
E11 bit = 1
TC1 bit = 0
E11 bit → 0 E11 bit → 1
TC1 bit = 0 TC1 bit = 0
E11 bit → 0
TC1 bit → 1
CPU CPU CPU CPU CPU DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU
Forcible termination of DMA channel
1 transfer
DMA channel 1
terminal count
Remark
The values of the DSAn, DDAn, and DBCn registers (n = 0 to 3) are retained even when DMA
transfer is forcibly stopped, because these registers are FIFO-configured buffer registers. The next
transfer condition can be set to these registers even while DMA transfer is in progress. On the other
hand, the setting of the DADCn and DCHCn registers is invalid during DMA transfer because these
registers are not buffer registers (see 6.8 Next Address Setting Function, 6.3.4 DMA
addressing control registers 0 to 3 (DADC0 to DADC3), and 6.3.5 DMA channel control
registers 0 to 3 (DCHC0 to DCHC3)).
User’s Manual U16031EJ4V1UD
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