MC68HC05X4 Datasheet, PDF (88/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Motorola CAN
Freescale Semiconductor, Inc.
MCAN bus timing
register 0 (CBT0)
Address: $0026
Bit 7
6
5
4
3
2
1
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1
Reset:
Undefined
Figure 10. MCAN Bus Timing 0 (CBT0)
Bit 0
BRP0
NOTE: This register can be accessed only when the RR bit in CCNTRL is set.
SJW1, SJW0 — Synchronization jump width bits
The synchronization jump width defines the maximum number of
system clock (t_SCL) cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 1).
Table 1. Synchronization jump width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization jump width
1 t_SCL cycle
2 t_SCL cycles
3 t_SCL cycles
4 t_SCL cycles
BRP5 – BRP0 — Baud rate prescaler bits
These bits determine the MCAN system clock cycle time (t_SCL), which
is used to build up the individual bit timing, according to Table 2 and
the formula in Figure 11.
Table 2. Baud rate prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler value (P)
1
2
3
4
:
:
64
MC68HC05X4
88
Motorola CAN
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