MC68HC05X4 Datasheet, PDF (123/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Programmable Timer
Timer state diagrams
Internal
processor clock
Internal
timer clocks
_TT0001
^T10
^T11
16-bit
counter
Output compare
register
Compare register
latch
Output compare
flag and TCMP
$F456
(Note 1)
CPU writes $F457
$F457
(Note 1)
(Note 2)
$F458
$F457
$F459
Note: (1) The CPU write to the compare registers may take place at any time, but a compare
only occurs at timer state T01. Thus a four cycle difference may exist between the write to
the compare register and the actual compare.
Note: (2) The output compare flag is set at the timer state T11 that follows the comparison
match ($F457 in this example).
Figure 14. Timer state timing diagram for output compare
Internal
processor clock
Internal
timer clocks
_T00


T01
^T10
^T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note: The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to
$0000). It is cleared by a read of the timer status register during the internal
processor clock high time, followed by a read of the counter low register.
Figure 15. Timer state timing diagram for timer overflow
15-ptimer
MOTOROLA
16-Bit Programmable Timer
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MC68HC05X4 Rev 1.0
123