MC68HC05X4 Datasheet, PDF (84/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Motorola CAN
Freescale Semiconductor, Inc.
RBS — Receive buffer status
This bit is set by the MCAN when a new message is available. When
clear this indicates that no message has become available since the
last RRB command. The bit is cleared when RRB is set. However, if
the second receive buffer already contains a message, then control of
that buffer is given to the CPU and RBS is immediately set again. The
first receive buffer is then available for the next incoming message
from the MCAN.
1 = Full – A new message is available for the CPU to read.
0 = Empty – No new message is available.
MCAN interrupt
register (CINT)
All bits of this register are read only; all are cleared by a read of the
register.
This register must be read in the interrupt handling routine in order to
enable further interrupts.
Address: $0023
Bit 7
6
5
4
3
2
1
Bit 0
WIF
OIF
EIF
TIF
RIF
External Reset: -
-
-
0
0
0
0
0
Reset: with RR bit set -
-
-
u
0
u
0
0
Figure 7. MCAN Interrupt Register (CINT)
WIF — Wake-up interrupt flag
If the MCAN detects bus activity whilst it is asleep, it clears the SLEEP
bit in the CCOM register; the WIF bit will then be set. WIF is cleared
by reading the MCAN interrupt register (CINT), or by an external
reset.
1 = MCAN has detected activity on the bus and requested
wake-up.
0 = No wake-up interrupt has occurred.
MC68HC05X4
84
Motorola CAN
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