MC68HC05X4 Datasheet, PDF (108/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Core Timer
Freescale Semiconductor, Inc.
Core timer counter
register (CTCR)
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
Figure 3. Core Timer Counter Register (CTCR)
The core timer counter register is a read-only register, which contains
the current value of the 8-bit ripple counter at the beginning of the timer
chain. Reset clears this register.
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains
active. If the CTIMER interrupts are enabled, then a CTIMER interrupt
will cause the processor to exit the WAIT mode.
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an external reset, the internal oscillator will
restart, followed by an internal processor stabilization delay (t_PORL). The
timer is then cleared and operation resumes.
MC68HC05X4 Rev 1.0
108
Core Timer
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6-ctimer
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