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MC68HC05X4 Datasheet, PDF (51/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
Resets, Interrupts and Low Power Modes
Interrupts
Maskable
hardware
interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts
(internal and external) are masked. Clearing the I-bit allows interrupt
processing to occur.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I-bit is cleared.
MCAN interrupt
(CIRQ)
Wired-OR
interrupt (WOI)
5-resets
MOTOROLA
Several sources can trigger a CIRQ. The MCAN interrupt register at
$0023 is used to identify the source. Each CIRQ source can be
individually enabled (except the wake-up interrupt, which is always
enabled) by different bits of the MCAN control register at $0020.
The CIRQ sources are (see also MCAN interrupt register (CINT)):
Receive IRQ: this signals successful reception of a complete message,
Transmit IRQ: this signals successful transmission of a complete
message,
Error IRQ: this is set when either the error status or bus status bits in the
MCAN status register change state (see MCAN status register
(CSTAT)),
Data Overrun: an incoming message on the bus cannot be received
because both receive buffers are tied up,
Wake-up IRQ: this signals activity on the bus while the MCAN is in
SLEEP mode.
CIRQ interrupts are serviced by the routine located at the address
specified by the contents of $1FFA and $1FFB.
An external WOI capability is provided on all I/O pins. When WOI is
enabled on a given pin (refer to Input/output programming and Port
A), an external interrupt is requested when this pin is pulled high. The
interrupt request is latched immediately following the rising edge of the
external WOI interrupt signal. It is then synchronised internally and
serviced by the interrupt routine whose start address is contained in
memory locations $1FF6 and $1FF7. The address of the latch bit for the
Resets, Interrupts and Low Power Modes
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MC68HC05X4 Rev 1.0
51