MC68HC05X4 Datasheet, PDF (120/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Programmable Timer
location $17 will not inhibit the compare function. The processor can
write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level
register whether the output compare flag (OCF) is set or clear. The
minimum time required to update the output compare register is a
function of the program rather than the internal hardware. Because the
output compare flag and the output compare register are not defined at
power on, and not affected by reset, care must be taken when initializing
output compare functions with software. The following procedure is
recommended:
1. write to output compare high to inhibit further compares;
2. read the timer status register to clear OCF (if set);
3. write to output compare low to enable the output compare
function.
All bits of the output compare register are readable and writable and are
not altered by the timer hardware or reset. If the compare function is not
needed, the two bytes of the output compare register can be used as
storage locations.
Timer during WAIT mode
All CPU action is suspended, but the timers (core and 16-bit) remain
active. An interrupt from either of the timers, if enabled, will cause the
MCU to exit WAIT mode.
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, hence the timer stops
counting. If STOP is exited by an interrupt the counter retains the last
count value. If the device is reset, then the counter is forced to $FFFC.
During STOP, if at least one valid input capture edge occurs at the TCAP
pin, the input capture detect circuit is armed. This does not set any timer
flags nor wake up the MCU. When the MCU does wake up, however,
there is an active input capture flag and data from the first valid edge that
MC68HC05X4 Rev 1.0
120
16-Bit Programmable Timer
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