MC68HC05X4 Datasheet, PDF (118/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Programmable Timer
bit (IEDG). The most significant 8 bits are stored in the input capture high
register at $14, the least significant in the input capture low register at
$15.
The result obtained from an input capture will be one greater than the
value of the free-running counter on the rising edge of the internal bus
clock preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles. The free-running counter
contents are transferred to the input capture register on each valid signal
transition whether the input capture flag (ICF) is set or clear. The input
capture register always contains the free-running counter value that
corresponds to the most recent input capture. After a read of the input
capture register MSB at location $14, the counter transfer is inhibited
until the LSB at location $15 is also read. This characteristic causes the
time used in the input capture software routine and its interaction with
the main program to determine the minimum pulse period. A read of the
input capture register LSB at location $15 does not inhibit the
free-running counter transfer since the two actions occur on opposite
edges of the internal bus clock.
Reset does not affect the contents of the input capture register, except
when exiting STOP mode.
MC68HC05X4 Rev 1.0
118
16-Bit Programmable Timer
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10-ptimer
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