MC68HC05X4 Datasheet, PDF (45/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
CPU
Instruction Set Summary
Table 6. Instruction Set Summary (Continued)
Source
Form
Operation
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
Description
(M) – $00
Effect on
CCR
H I NZC
DIR 3D ^dd 4
INH 4D
3
— — ¤ ¤ — INH 5D
3
IX1 6D ff 5
IX 7D
4
TXA
Transfer Index Register to Accumulator
A ← (X)
— — — — — INH 9F
2
WAIT
Stop CPU Clock and Enable Interrupts
—
0
◊
———
INH
8F
2
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel Relative program counter offset byte
rr Relative program counter offset byte
SP Stack pointer
X Index register
Z Zero flag
# Immediate value
∧ Logical AND
∨ Logical OR
⊕ Logical EXCLUSIVE OR
( ) Contents of
–( ) Negation (two’s complement)
← Loaded with
? If
: Concatenated with
¤ Set or cleared
— Not affected
19-cpu
MOTOROLA
CPU
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MC68HC05X4 Rev 1.0
45