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MC9S12B128_05 Datasheet, PDF (83/132 Pages) Motorola, Inc – Covers also preliminary MC9S12B64 using MC9S12B128 die
Device User Guide —9S12B128DGV1/D V01.13
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings1
Num
Rating
Symbol
Min
Max Unit
1 I/O, Regulator and Analog Supply Voltage
VDD5
-0.3
6.5
V
2 Internal Logic Supply Voltage 2
VDD
-0.3
3.0
V
3 PLL Supply Voltage 2
VDDPLL
-0.3
3.0
V
4 Voltage difference VDDX to VDDR and VDDA
∆VDDX
-0.3
0.3
V
5 Voltage difference VSSX to VSSR and VSSA
∆VSSX
-0.3
0.3
V
6 Digital I/O Input Voltage
VIN
-0.3
6.5
V
7 Analog Reference
VRH, VRL
-0.3
6.5
V
8 XFC, EXTAL, XTAL inputs
VILV
-0.3
3.0
V
9 TEST input
VTEST
-0.3
10.0
V
Instantaneous Maximum Current
10 Single pin limit for all digital I/O pins 3
ID
-25
+25
mA
Instantaneous Maximum Current
11 Single pin limit for XFC, EXTAL, XTAL4
I
DL
-25
+25
mA
Instantaneous Maximum Current
12 Single pin limit for TEST 5
IDT
-0.25
0
mA
15 Storage Temperature Range
Tstg
– 65
155
°C
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
4. Those pins are internally clamped to VSSPLL and VDDPLL.
5. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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