MC9S12B128_05 Datasheet, PDF (52/132 Pages) Motorola, Inc – Covers also preliminary MC9S12B64 using MC9S12B128 die

Device User Guide — 9S12B128DGV1/D V01.13
2.1.1 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function1
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
BKGD
PAD[15:8]
PAD[07:00]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ7
PJ6
PJ[1:0]
Pin Name
Function2
—
—
—
—
—
—
TAGHI
AN[15:8]
AN[07:00]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
KWJ6
KWJ[1:0]
Pin Name
Function
3
Pin Name
Function
4
Powered
by
Internal Pull
Resistor
CTRL
Reset
State
Description
—
—
VDDPLL
—
—
Oscillator Pins
—
—
VDDR
External Reset
None None
—
—
N.A.
Test Input
—
—
VDDX
Voltage Regulator Enable Input
—
—
VDDPLL
PLL Loop Filter
MODC
—
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
—
—
Port AD Inputs, Analog Inputs
AN[15:8] of ATD
VDDA None None
—
—
Port AD Inputs, Analog Inputs
AN[7:0] of ATD
—
—
—
—
PUCR/
PUPAE
PUCR/
PUPBE
Port A I/O, Multiplexed Address/Data
Disabled
Port B I/O, Multiplexed Address/Data
XCLKS
—
PUCR/
PUPEE
Up Port E I/O, Access, Clock Select
MODB
—
MODA
—
While RESET pin Port E I/O, Pipe Status, Mode Input
is low:
Down
Port E I/O, Pipe Status, Mode Input
—
—
Mode ^{Port E I/O, Bus Clock Output}
TAGLO
—
depende _{Port E I/O, Byte Strobe, Tag Low}
—
—
PUCR/
VDDR _PUPEE
nt¹ _{Port E I/O, R/W in expanded modes}
—
—
Port E Input, Maskable Interrupt
—
—
Up
Port E Input, Non Maskable Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
—
—
PERH/
PPSH
Port H I/O, Interrupt
Disabled
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
SCL
SDA
—
—
Port J I/O, Interrupt, SCL of IIC,
—
VDDX
PERJ/
PPSJ
Up Port J I/O, Interrupt, SDA of IIC,
—
Port J I/O, Interrupts
52