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MC9S12B128_05 Datasheet, PDF (109/132 Pages) Motorola, Inc – Covers also preliminary MC9S12B64 using MC9S12B128 die
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A.5 Reset, Oscillator and PLL
Device User Guide —9S12B128DGV1/D V01.13
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-19 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-19 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
Typ
1 D Reset input pulse width, minimum input time
PWRSTL
2
2 D Startup from Reset
nRST
192
3 D Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ
20
4 D Wait recovery startup time
tWRS
5 T Voltage Regulator Return from Pseudo Stop
tvup
Max
196
14
100
Unit
tosc
nosc
ns
tcyc
µs
A.5.1.1 POR
The release level VPORD (see Table A-17) and the assert level VPORA (see Table A-17) are derived from
the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the
oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the
MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.5.1.2 LVR
The assert level VLVRA (see Table A-17) is derived from the VDD Supply. After releasing the LVR reset
the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected,
the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.5.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.4 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
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