MC9S12B128_05 Datasheet, PDF (69/132 Pages) Motorola, Inc – Covers also preliminary MC9S12B64 using MC9S12B128 die

Device User Guide —9S12B128DGV1/D V01.13
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address
Interrupt Source
CCR
Mask
Local Enable
$FFFE, $FFFF
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register None
to determine reset source)
None
$FFFC, $FFFD
Clock Monitor fail reset
None PLLCTL (CME, SCME)
$FFFA, $FFFB
COP failure reset
None
COP rate select
$FFF8, $FFF9
Unimplemented instruction trap
None
None
$FFF6, $FFF7
SWI
None
None
$FFF4, $FFF5
XIRQ
X-Bit
None
$FFF2, $FFF3
IRQ
I-Bit
IRQCR (IRQEN)
$FFF0, $FFF1
Real Time Interrupt
I-Bit
CRGINT (RTIE)
$FFEE, $FFEF
Standard Timer channel 0
I-Bit
TIE (C0I)
$FFEC, $FFED
Standard Timer channel 1
I-Bit
TIE (C1I)
$FFEA, $FFEB
Standard Timer channel 2
I-Bit
TIE (C2I)
$FFE8, $FFE9
Standard Timer channel 3
I-Bit
TIE (C3I)
$FFE6, $FFE7
Standard Timer channel 4
I-Bit
TIE (C4I)
$FFE4, $FFE5
Standard Timer channel 5
I-Bit
TIE (C5I)
$FFE2, $FFE3
Standard Timer channel 6
I-Bit
TIE (C6I)
$FFE0, $FFE1
Standard Timer channel 7
I-Bit
TIE (C7I)
$FFDE, $FFDF
Standard Timer overflow
I-Bit
TMSK2 (TOI)
$FFDC, $FFDD
Pulse accumulator A overflow
I-Bit
PACTL (PAOVI)
$FFDA, $FFDB
Pulse accumulator input edge
I-Bit
PACTL (PAI)
$FFD8, $FFD9
SPI0
I-Bit
SPICR1 (SPIE, SPTIE)
$FFD6, $FFD7
SCI0
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD4, $FFD5
SCI1
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3
ATD
I-Bit
ATDCTL2 (ASCIE)
$FFD0, $FFD1
Reserved
I-Bit
Reserved
$FFCE, $FFCF
Port J
I-Bit
PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
HPRIO Value
to Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
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