MC9S12B128_05 Datasheet, PDF (105/132 Pages) Motorola, Inc – Covers also preliminary MC9S12B64 using MC9S12B128 die

A.4 VREG_3V3
A.4.1 Operating Conditions
Device User Guide —9S12B128DGV1/D V01.13
Table A-17 VREG_3V3 - Operating Conditions
Conditions are shown in Table A-4 unless otherwise noted
Num C
Characteristic
Symbol
1
P Input Voltages
V_VDDR,A
Min Typical Max Unit
2.97
—
5.5
V
Output Voltage Core
3
P
Full Performance Mode
Reduced Power Mode
Shutdown Mode
V_DD
2.35
2.5
1.6
2.5
2.75
V
2.75
V
—
—¹
—
V
Output Voltage PLL
Full Performance Mode
2.35
2.5
2.75
4
P
Reduced Power Mode²
V_DDPLL
1.7
Reduced Power Mode³
1.4
Shutdown Mode
—
2.5
2.5
—⁴
2.75
V
V
2.75
V
—
Low Voltage Interrupt⁵
7
P
Assert Level
Deassert Level
V_LVIA
V_LVID
4.0
4.37
4.66
V
4.15
4.52
4.77
V
8
P
Low Voltage Reset⁶
Assert Level
V_LVRA
2.25
—
—
V
Power-on Reset⁷
9
C
Assert Level
Deassert Level
V_PORA
0.97
—
—
V
V_PORD
—
—
2.05
V
NOTES:
1. High Impedance Output
2. Current IDDPLL = 0.5mA (Colpitts Oscillator)
3. Current IDDPLL = 3mA (Pierce Oscillator)
4. High Impedance Output
5. Monitors V_DDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
6. Monitors V_DD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-3)
7. Monitors V_DD. Active in all modes.
A.4.2 Chip Power-up and Voltage Drops
VREG_3V3 sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Their function is described in Figure A-3.
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