MC68HC705C8A Datasheet, PDF (64/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets
CM1:CM0
00
01
10
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Table 5-1. Programmable COP Timeout Period Selection
COP
Timeout Rate
f_OP ÷ 2¹⁵
f_OP ÷ 2¹⁷
f_OP ÷ 2¹⁹
f_OP ÷ 2²¹
f_OSC = 4.0 MHz
f_OP = 2.0 MHz
16.38 ms
65.54 ms
262.14 ms
1.048 s
Programmable COP Timeout Period
f_OSC = 3.5795 MHz f_OSC = 2.0 MHz
f_OP = 1.7897 MHz f_OP = 1.0 MHz
18.31 ms
32.77 ms
73.24 ms
131.07 ms
292.95 ms
524.29 ms
1.172 s
2.097 s
f_OSC = 1.0 MHz
f_OP = 0.5 MHz
65.54 ms
262.14 ms
1.048 s
4.194 s
5.3.3.2 Non-Programmable COP Watchdog
A timeout of the 18-stage ripple counter in the non-programmable COP
watchdog generates a reset. The timeout period is 65.536 ms when
f_OSC = 4 MHz. The timeout period for the non-programmable COP timer
is a direct function of the crystal frequency. The equation is:
262,144
Timeout period =
f_OSC
Two memory locations control operation of the non-programmable COP
watchdog:
1. Non-programmable COP enable bit (NCOPE) in mask option
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See 9.5.3 Mask Option
Register 2.
NOTE:
Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOPE bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
Technical Data
64
Resets
MC68HC705C8A — Rev. 2.0
MOTOROLA