MC68HC705C8A Datasheet, PDF (55/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
Interrupt Processing
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
1. Stores the CPU registers on the stack in the order shown in
Figure 4-4
2. Sets the I bit in the CCR to prevent further interrupts
3. Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Reset
Software
interrupt
(SWI)
External
interrupt
Timer
interrupts
SCI
interrupts
SPI
interrupts
Source
Power-on
logic
RESET pin
User code
IRQ pin
Port B pins
ICF bit
OCF bit
TOF bit
TDRE bit
TC bit
RDRF bit
OR bit
IDLE bit
SPIF bit
MODF bit
Local
Mask
None
None
None
ICIE bit
OCIE bit
TOIE bit
TCIE bit
RIE bit
ILIE bit
SPIE
Global
Mask
None
None
I bit
I bit
I bit
I bit
Priority
(1 = Highest)
1
Same priority
as any
instruction
2
3
4
5
Vector Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-4.
MC68HC705C8A — Rev. 2.0
MOTOROLA
Interrupts
Technical Data
55