MC68HC705C8A Datasheet, PDF (147/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.1 SPI Data Register
The SPDR shown in Figure 11-7 is the read buffer for characters
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
11.9.2 SPI Control Register
• Enables SPI interrupt requests
• Enables the SPI
• Configures the SPI as master or slave
• Selects serial clock polarity, phase, and frequency
Address: $000A
Bit 7
6
5
4
3
2
1
Read:
SPIE SPE
Write:
MSTR CPOL CPHA SPR1
Reset: 0
0
0
U
U
U
= Unimplemented
U = Unaffected
Figure 11-8. SPI Control Register (SPCR)
Bit 0
SPR0
U
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
MC68HC705C8A — Rev. 2.0
MOTOROLA
Serial Peripheral Interface (SPI)
Technical Data
147