MC68HC705C8A Datasheet, PDF (182/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

t_VDDR
V_DD
V_DD THRESHOLD (1-2 V TYPICAL)
OSC1^*
t_OXOV
t_CYC
INTERNAL
PROCESSOR
CLOCK
INTERNAL
ADDRESS
BUS **
1FFE
1FFF
NEW PC
1FFE
1FFE
1FFE
1FFE
INTERNAL
DATA
BUS ***
NEW
NEW
OP
PCH
PCL
CODE
PCH
t_RL
RESET
***
* OSC1 line is not meant to represent frequency. It is only used to represent time.
** Internal timing signal and bus information are not available externally.
***The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
1FFF
NEW PC
PCL
OP
CODE
Figure 13-7. Power-On Reset and External Reset Timing Diagram