MC68HC705C8A Datasheet, PDF (50/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
EDGE- AND LEVEL-SENSITIVE TRIGGER
OPTION REGISTER
V_DD
D
Q
IRQ LATCH
I BIT (CCR)
EXTERNAL
INTERRUPT
REQUEST
INTERRUPT PIN
C
Q
R
POR
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
Figure 4-1. External Interrupt Internal Function Diagram
IRQ PIN
t_ILIL
t_ILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t_ILIH) is either 125 ns (f_OP = 2.1 MHz)
or 250 ns (f_OP = 1 MHz). The period t_ILIL should not be less than the number of t_CYC cycles it takes to
execute the interrupt service routine plus 19 t_CYC cycles.
IRQ₁
.
t_ILIH
.
NORMALLY
.
USED WITH
IRQ_n
WIRED-OR
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
CPU continues to recognize an interrupt.
Figure 4-2. External Interrupt Timing
Technical Data
50
Interrupts
MC68HC705C8A — Rev. 2.0
MOTOROLA