MC68HC705C8A Datasheet, PDF (123/222 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Communications Interface (SCI)
SCI Operation
Addr.
$000D
$000E
$000F
$0010
$0011
Register Name
Bit 7
6
5
4
3
Baud Rate Register ^Read:
(Baud) Write:
SCP1 SCP0
See page 134. _{Reset: U}
U
0
0
U
SCI Control Register 1 ^Read: _R8
T8
(SCCR1) Write:
See page 128. _{Reset: U}
U
M
WAKE
U
U
SCI Control Register 2 ^Read: _TIE
TCIE
RIE
ILIE
TE
(SCCR2) Write:
See page 129. _{Reset: 0}
0
0
0
0
SCI Status Register ^{Read: TDRE}
TC
RDRF
IDLE
OR
(SCSR) Write:
See page 131. _{Reset: 1}
1
0
0
0
SCI Data Register ^Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
(SCDR) Write:
See page 127. _Reset:
Unaffected by reset
= Unimplemented U = Unaffected
2
SCR2
U
RE
0
NF
0
Bit 2
1
Bit 0
SCR1 SCR0
U
U
RWU SBK
0
0
FE
0
U
Bit 1 Bit 0
Figure 10-3. SCI Transmitter I/O Register Summary
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2)
and then writing data to the SCDR begins the transmission. At the
start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After
the preamble shifts out, the control logic transfers the SCDR data
into the shift register. A logic 0 start bit automatically goes into the
least significant bit (LSB) position of the shift register, and a logic
1 stop bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
MC68HC705C8A — Rev. 2.0
MOTOROLA
Serial Communications Interface (SCI)
Technical Data
123