N25Q00AA11GSF40F Datasheet, PDF (7/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Device Description
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after power-up,
nonvolatile configuration register bit settings can enable XIP as the default mode.
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile
configuration register for default and/or nonvolatile settings. Volatile settings can be
configured through the volatile and volatile-enhanced configuration registers. These
configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI)
• Required XIP mode
• Enabling/disabling HOLD (RESET function)
• Enabling/disabling wrap mode
Figure 1: Logic Diagram
V_CC
DQ0
C
S#
V_PP/W#/DQ2
HOLD#/DQ3
NOR die 4
NOR die 3
NOR die 2
DQ1
NOR die 1
V_SS
Note: 1. Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
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