N25Q00AA11GSF40F Datasheet, PDF (30/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Command Definitions
Table 18: Command Set (Continued)
Note 1 applies to entire table
Command
Code
ONE-TIME PROGRAMMABLE (OTP) Operations
READ OTP ARRAY
4Bh
PROGRAM OTP ARRAY
42h
4-BYTE ADDRESS MODE Operations
ENTER 4-BYTE ADDRESS MODE
B7h
EXIT 4-BYTE ADDRESS MODE
E9h
Extended
Yes
Yes
Dual
I/O
Yes
Yes
Quad
I/O
Yes
Yes
Data
Bytes
1 to 64
0
Notes
5
4, 13, 14
2, 13
Notes: 1. Yes in the protocol columns indicates that the command is supported and has the same
functionality and command sequence as other commands marked Yes.
2. Address bytes = 0. Dummy clock cycles = 0.
3. Address bytes = 3. Dummy clock cycles default = 8.
4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0.
5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy
clock cycles are configurable by the user.
6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy
clock cycles are configurable by the user.
7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 8. Dummy clock cycles are configurable by the user.
8. Address bytes = 4. Dummy clock cycles = 0.
9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10
(when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user.
10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable
by the user.
11. When the device is in dual SPI protocol, the command can be entered with any of these
three codes. The different codes enable compatibility between dual SPI and extended
SPI protocols.
12. When the device is in quad SPI protocol, the command can be entered with any of these
three codes. The different codes enable compatibility between quad SPI and extended
SPI protocols.
13. The WRITE ENABLE command must be issued first before this command can be execu-
ted.
14. Requires the READ FLAG STATUS REGISTER command being issued with at least one byte
output. (After code, at least 8 clock pulses in extended SPI, 4 clock pulses in dual I/O SPI,
and 2 clock pulses in quad I/O SPI.) The cycle is not complete until bit 7 of the flag status
register outputs 1.
15. The end of operation can be detected by means of a READ FLAG STATUS REGISTER com-
mand being issued four times, S# toggled between each command execution, and bit 7
of the flag status register outputs 1 for all four READ operations.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
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