N25Q00AA11GSF40F Datasheet, PDF (36/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
READ REGISTER and WRITE REGISTER Operations
Table 19: Lock Register
Note 1 applies to entire table
Bit Name
7:2 Reserved
1
Write lock down
0
Sector write lock
Settings
Description
0
Bit values are 0.
0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,
1 = Set
which means sector lock down and sector write lock bits can be
set.
When this bit set, neither of the lock register bits can be written
to until the next power cycle.
0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,
1 = Set
which means that PROGRAM and ERASE operations in this sector
can be executed and sector content modified.
When this bit is set, PROGRAM and ERASE operations in this sec-
tor will not be executed.
Note: 1. Sector lock register bits 1:0 are written to by the WRITE LOCK REGISTER command. The
command will not execute unless the sector lock down bit is cleared.
Figure 11: READ LOCK REGISTER Command
Extended
0
C
DQ[0]
DQ1
Command
MSB
High-Z
7
8
LSB
A[MAX]
Dual
0
C
DQ[1:0]
Command
MSB
3
4
LSB
A[MAX]
C_x
A[MIN]
D_OUT
MSB
C_x
D_OUT
A[MIN]
D_OUT
MSB
D_OUT
D_OUT
D_OUT
D_OUT
D_OUT
D_OUT
LSB
D_OUT
D_OUT
D_OUT
LSB
D_OUT
D_OUT
Quad
C
0
1
2
C_x
DQ[3:0]
Command
MSB
LSB
A[MAX]
A[MIN]
D_OUT
MSB
LSB
D_OUT
D_OUT
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C_x = 1 + ((A[MAX] + 1)/4).
Don’t Care
WRITE LOCK REGISTER Command
To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must
be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until
the eighth bit of the last data byte has been latched in, after which it must be driven
HIGH. The command code is input on DQn, followed by address bytes that point to a
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
36
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