N25Q00AA11GSF40F Datasheet, PDF (68/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
ONE-TIME PROGRAMMABLE Operations
PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one
OTP control byte. When the operation is in progress, the write in progress bit is set to 1.
The write enable latch bit is cleared to 0, whether the operation is successful or not, and
the status register and flag status register can be polled for the operation status. When
the operation completes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and the program fail bit is
set to 1. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1. The operation is considered
complete once bit 7 of the flag status register outputs 1 with at least one byte output.
The OTP control byte (byte 64) is used to permanently lock the OTP memory array.
Table 31: OTP Control Byte (Byte 64)
Bit Name
0 OTP control byte
Settings
0 = Locked
1 = Unlocked (Default)
Description
Used to permanently lock the 64-byte OTP array. When bit 0 = 1,
the 64-byte OTP array can be programmed. When bit 0 = 0, the
64-byte OTP array is read only.
Once bit 0 has been programmed to 0, it can no longer be
changed to 1. Program OTP array is ignored, the write enable
latch bit remains set, and flag status register bits 1 and 4 are set.
Figure 35: PROGRAM OTP Command
Extended
0
C, C_1, C_2
DQ0/DQ4
Command
MSB
Dual
0
C, C_1, C_2
DQ[1:0]/DQ[6:5]
Command
MSB
7
8
LSB
A[MAX]
3
4
LSB
A[MAX]
Quad
C, C_1, C_2
0
1
2
DQ[3:0]/DQ[7:4]
Command
MSB
LSB
A[MAX]
C_x
A[MIN]
D_IN
MSB
C_x
A[MIN]
D_IN
MSB
C_x
A[MIN]
D_IN
MSB
D_IN
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
LSB
D_IN
D_IN
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + (A[MAX] + 1)/2.
For quad SPI protocol, C_x = 1 + (A[MAX] + 1)/4.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.