N25Q00AA11GSF40F Datasheet, PDF (37/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
READ REGISTER and WRITE REGISTER Operations
location in the sector, and then one data byte that contains the desired settings for lock
register bits 0 and 1.
When execution is complete, the write enable latch bit is cleared within ^tSHSL2 and no
error bits are set. Because lock register bits are volatile, change to the bits is immediate.
WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef-
fect. After the data is latched in, S# must be driven HIGH.
Figure 12: WRITE LOCK REGISTER Command
Extended
0
C
DQ0
Command
MSB
Dual
0
C
DQ[1:0]
Command
MSB
7
8
LSB
A[MAX]
3
4
LSB
A[MAX]
Quad
0
C
DQ[3:0]
Command
MSB
1
2
LSB
A[MAX]
C_x
A[MIN]
D_IN
MSB
C_x
A[MIN]
D_IN
MSB
C_x
A[MIN]
D_IN
MSB
D_IN
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
LSB
D_IN
D_IN
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C_x = 1 + ((A[MAX] + 1)/4).
CLEAR FLAG STATUS REGISTER Command
To execute the CLEAR FLAG STATUS REGISTER command and clear the error bits
(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-
mand code is input on DQ0. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation
is terminated by driving S# HIGH at any time.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
37
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