N25Q00AA11GSF40F Datasheet, PDF (63/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

1Gb, 3V, Multiple I/O Serial NOR Flash Memory
ERASE Operations
byte output. When the operation completes, the program or erase controller bit is
cleared to 1.
The command is not executed if any sector is locked. Instead, the write enable latch bit
remains set to 1, and flag status register bits 1 and 5 are set.
Figure 32: DIE ERASE Command
Extended
C
DQ0
Dual
C
DQ0[1:0]
Quad
C
DQ0[3:0]
0
7
8
Command
MSB
0
LSB
A[MAX]
3
4
Command
MSB
0
LSB
A[MAX]
1
2
MSB
Command
LSB
A[MAX]
C_x
A[MIN]
C_x
A[MIN]
C_x
A[MIN]
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + (A[MAX] + 1)/2.
For quad SPI protocol, C_x = 1 + (A[MAX] + 1)/4.
PROGRAM/ERASE SUSPEND Command
To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The com-
mand code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RE-
SUME command.
PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt
and suspend an array PROGRAM or ERASE operation within the program/erase latency.
If a SUSPEND command is issued during a PROGRAM operation, then the flag status
register bit 2 is set to 1. After erase/program latency time, the flag status register bit 7 is
also set to 1, but the device is considered in suspended state once bit 7 of the flag status
register outputs 1 with at least one byte output. In the suspended state, the device is
waiting for any operation. (See the Operations Allowed/Disallowed During Device
States table.)
If a SUSPEND command is issued during an ERASE operation, then the flag status regis-
ter bit 6 is set to 1. After erase/program latency time, the flag status register bit 7 is also
set to 1, but the device is considered in suspended state once bit 7 of the flag status reg-
ister outputs 1 with at least one byte output. In the suspended state, the device is wait-
ing for any operation. (See the Operations Allowed/Disallowed During Device States ta-
ble.)
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
63
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