N25Q00AA11GSF40F Datasheet, PDF (66/89 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

RESET Operations
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
RESET Operations
Table 30: Reset Command Set
Command
RESET ENABLE
RESET MEMORY
Command Code (Binary)
0110 0110
1001 1001
Command Code (Hex)
66
99
Address Bytes
0
0
RESET ENABLE and RESET MEMORY Command
To reset the device, the RESET ENABLE command must be followed by the RESET
MEMORY command. To execute each command, S# is driven LOW. The command code
is input on DQ0. A minimum de-selection time of ^tSHSL2 must come between the RE-
SET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these
two commands are executed and S# is driven HIGH, the device enters a power-on reset
condition. A time of ^tSHSL3 is required before the device can be re-selected by driving
S# LOW. It is recommended that the device exit XIP mode before executing these two
commands to initiate a reset.
If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or
suspended, the operation is aborted and data may be corrupted.
Figure 33: RESET ENABLE and RESET MEMORY Command
01234567
C
Reset enable
S#
01234567
Reset memory
DQ0
Note: 1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.
RESET Conditions
All volatile lock bits, the volatile configuration register, the enhanced volatile configura-
tion register, and the extended address register are reset to the power-on reset default
condition. The power-on reset condition depends on settings in the nonvolatile config-
uration register.
Reset is effective once bit 7 of the flag status register outputs 1 with at least one byte
output. A RESET ENABLE command is not accepted in the cases of WRITE STATUS
REGISTER and WRITE NONVOLATILE CONFIGURATION REGISTER operations.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
66
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