PIC16F87 Datasheet, PDF (92/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Read
Internal
Data Bus
Write
SSPBUF reg
RB1/SDI/SDA
RB2/SDO/RX/DT
SSPSR reg
bit0
Shift
Clock
RB5/SS/
TX/CK
RB4/SCK/
SCL
SS Control
Enable
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
TRISB<4>
TMR2 Output
2
Prescaler TCY
4, 16, 64
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISB register)
appropriately programmed. That is:
• SDI must have TRISB<1> set
• SDO must have TRISB<2> cleared
• SCK (Master mode) must have TRISB<4>
cleared
• SCK (Slave mode) must have TRISB<4> set
• SS must have TRISB<5> set
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to VDD.
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pin control must be
enabled.
3: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of SS pin can affect the state
read back from the TRISB<5> bit. The
peripheral OE signal from the SSP module
into PORTB controls the state that is read
back from the TRISB<5> bit. If read-
modify-write instructions, such as BSF, are
performed on the TRISB register while the
SS pin is high, this will cause the
TRISB<5> bit to be set, thus disabling the
SDO output.
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh,8Bh INTCON
10Bh,18Bh
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch
PIR1
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
8Ch
PIE1
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h
SSPSTAT SMP CKE D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS30487B-page 90
Preliminary
 2003 Microchip Technology Inc.