PIC16F87 Datasheet, PDF (43/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
FIGURE 4-6:
PIC16F87/88 CLOCK DIAGRAM
OSC2
OSC1
T1OSO
T1OSI
Primary Oscillator
SLEEP
Secondary Oscillator
T1OSCEN
Enable
Oscillator
Internal
Oscillator
Block
31.25 kHz
Source
8 MHz
(INTOSC)
31.25 kHz
(INTRC)
Config1(FOSC2:FOSC0)
SCS<1:0>(T1OSC)
LP, XT, HS, RC, EC
T1OSC
To Timer1
OSCCON<6:4>
8 MHz
111
4 MHz
110
2 MHz
101
1 MHz
100
500 kHz
011
250 kHz
010
125 kHz
001
31.25 kHz
000
Internal Oscillator
Peripherals
CPU
WDT, FSCM
4.6.4 MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time, regardless
of which clock source is currently being used as the sys-
tem clock. The internal oscillator allows users to change
the frequency during run time. This is achieved by mod-
ifying the IRCF bits in the OSCCON register. The
sequence of events that occur after the IRCF bits are
modified is dependent upon the initial value of the IRCF
bits before they are modified. If the INTRC (31.25 kHz,
IRCF<2:0> = 000) is running and the IRCF bits are
modified to any other value than ‘000’, a 4 ms clock
switch delay is turned on. Code execution continues at
a higher than expected frequency while the new fre-
quency stabilizes. Time sensitive code should wait for
the IOFS bit in the OSCCON register to become set
before continuing. This bit can be monitored to ensure
that the frequency is stable before using the system
clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz IRCF<2:0> ≠ 000), there is no need for a
4 ms clock switch delay. The new INTOSC frequency
will be stable immediately after the eight falling edges.
The IOFS bit will remain set after clock switching
occurs.
Note:
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a fre-
quency that may be out of the VDD specifi-
cation range; for example, VDD = 2.0V and
IRCF = 111 (8 MHz).
4.6.5 CLOCK TRANSITION SEQUENCE
Following are three different sequences for switching
the internal RC oscillator frequency.
• Clock before switch: 31.25 kHz (IRCF<2:0> = 000)
1. IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is clear to indicate that the clock is
unstable and a 4 ms delay is started. Time
dependent code should wait for IOFS to become
set.
5. Switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> ≠ 000)
1. IRCF bits are modified to INTRC
(IRCF<2:0> = 000).
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. Oscillator switchover is complete.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 41