PIC16F87 Datasheet, PDF (208/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

P IC 1 6 F 8 7 /8 8
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T1CKPS0 Bit ...................................................................... 72
T1CKPS1 Bit ...................................................................... 72
T1CON Register ................................................................. 14
T1OSCEN Bit ..................................................................... 72
T1SYNC Bit ........................................................................ 72
T2CKPS0 Bit ...................................................................... 80
T2CKPS1 Bit ...................................................................... 80
T2CON Register ................................................................. 14
TAD ................................................................................... 118
Time-out Sequence .......................................................... 134
Timer0 ................................................................................ 67
Associated Registers ................................................. 69
Clock Source Edge Select (T0SE Bit) ........................ 18
Clock Source Select (T0CS Bit) ................................. 18
External Clock ............................................................ 68
Interrupt ...................................................................... 67
Operation ................................................................... 67
Overflow Enable (TMR0IE Bit) ................................... 19
Overflow Flag (TMR0IF Bit) ..................................... 140
Overflow Interrupt ..................................................... 140
Prescaler .................................................................... 68
T0CKI ......................................................................... 68
Timer1 ................................................................................ 71
Associated Registers ................................................. 77
Asynchronous Counter Mode ..................................... 74
Reading and Writing .......................................... 74
Capacitor Selection .................................................... 75
Counter Operation ...................................................... 73
Operation ................................................................... 71
Operation in Timer Mode ........................................... 73
Oscillator .................................................................... 75
Oscillator Layout Considerations ............................... 75
Prescaler .................................................................... 76
Resetting Timer1 Register Pair .................................. 76
Resetting Timer1 Using a CCP Trigger Output .......... 75
Synchronized Counter Mode ...................................... 73
Use as a Real-Time Clock ......................................... 76
Timer2 ................................................................................ 79
Associated Registers ................................................. 80
Output ........................................................................ 79
Postscaler .................................................................. 79
Prescaler .................................................................... 79
Prescaler and Postscaler ........................................... 79
Timing Diagrams
A/D Conversion ........................................................ 189
Asynchronous Master Transmission ........................ 103
Asynchronous Master Transmission
(Back to Back) .................................................. 103
Asynchronous Reception ......................................... 104
Asynchronous Reception with
Address Byte First ............................................ 107
Asynchronous Reception with Address Detect ........ 107
Brown-out Reset ...................................................... 179
Capture/Compare/PWM (CCP1) .............................. 181
CLKO and I/O ........................................................... 178
External Clock .......................................................... 177
Fail-Safe Clock Monitor ............................................ 144
I²C Bus Data ............................................................ 185
I²C Bus START/STOP Bits ...................................... 184
I²C Reception (7-bit Address) .................................... 94
I²C Transmission (7-bit Address) ............................... 94
Primary System Clock after RESET
(EC, RC, INTRC) ............................................... 48
Primary System Clock after RESET (HS, XT, LP) ..... 47
PWM Output .............................................................. 84
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 179
Slow Rise Time (MCLR Tied to VDD
Through RC Network) ...................................... 138
SPI Master Mode ....................................................... 91
SPI Master Mode (CKE = 0, SMP = 0) .................... 182
SPI Master Mode (CKE = 1, SMP = 1) .................... 182
SPI Slave Mode (CKE = 0) .................................91, 183
SPI Slave Mode (CKE = 1) .................................91, 183
Switching to SEC_RUN Mode ................................... 44
Synchronous Reception (Master Mode, SREN) ...... 111
Synchronous Transmission ..................................... 109
Synchronous Transmission (Through TXEN) .......... 109
Time-out Sequence on Power-up (MCLR Tied
to VDD Through Pull-up Resistor) .................... 137
Time-out Sequence on Power-up (MCLR Tied
to VDD Through RC Network): Case 1 ............. 137
Time-out Sequence on Power-up (MCLR Tied
to VDD Through RC Network): Case 2 ............. 137
Timer0 and Timer1 External Clock .......................... 180
Timer1 Incrementing Edge ........................................ 73
Transition Between SEC_RUN/RC_RUN
and Primary Clock ............................................. 46
Two-Speed Start-up Mode ....................................... 143
USART Synchronous Receive (Master/Slave) ........ 187
USART Synchronous Transmission
(Master/Slave) ................................................. 187
Wake-up from SLEEP via Interrupt .......................... 146
XT, HS, LP, EC and EXTRC to RC_RUN Mode ........ 43
Timing Parameter Symbology .......................................... 176
Timing Requirements
A/D Conversion ........................................................ 189
Capture/Compare/PWM (CCP1) ............................. 181
CLKO and I/O .......................................................... 178
External Clock .......................................................... 177
I²C Bus Data ............................................................ 186
I²C Bus START/STOP Bits ...................................... 185
RESET, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer and
Brown-out Reset .............................................. 179
SPI Mode ................................................................. 184
Timer0 and Timer1 External Clock .......................... 180
USART Synchronous Receive ................................. 187
USART Synchronous Transmission ........................ 187
TMR0 Register ................................................................... 14
TMR1CS Bit ....................................................................... 72
TMR1H Register ................................................................ 14
TMR1L Register ................................................................. 14
TMR1ON Bit ....................................................................... 72
TMR2 Register ................................................................... 14
TMR2ON Bit ....................................................................... 80
TMRO Register .................................................................. 16
TOUTPS0 Bit ..................................................................... 80
TOUTPS1 Bit ..................................................................... 80
TOUTPS2 Bit ..................................................................... 80
TOUTPS3 Bit ..................................................................... 80
TRISA Register .............................................................15, 51
TRISB Register .................................................................. 15
Two-Speed Clock Start-up Mode ..................................... 143
Two-Speed Start-up ......................................................... 129
TXREG Register ................................................................ 14
DS30487B-page 206
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