PIC16F87 Datasheet, PDF (75/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
7.2 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON<2>), has no effect since the internal clock is
always in sync.
7.3 Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
7.4 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RB7/AN6/PGD/T1OSI, when bit
T1OSCEN is set, or on pin RB6/AN5/PGC/T1OSO/
T1CKI, when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 7-1:
T1CKI
(Default High)
TIMER1 INCREMENTING EDGE
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
FIGURE 7-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
T1OSO/T1CKI
T1OSI
TMR1
0
Synchronized
Clock Input
TMR1H TMR1L
1
T1OSC
TMR1ON
On/Off
T1SYNC
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
Synchronize
det
Q Clock
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 73