PIC16F87 Datasheet, PDF (189/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
FIGURE 18-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RB5/TX/CK
pin
RB2/RX/DT
pin
121
121
120
122
Note: Refer to Figure 18-3 for load conditions.
TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units Conditions
120
TckH2dtV SYNC XMIT (MASTER &
PIC16F87/88
SLAVE)
Clock high to data out valid
PIC16LF87/88
—
— 80 ns
—
— 100 ns
121
Tckrf
Clock out rise time and fall time PIC16F87/88
(Master mode)
PIC16LF87/88
—
— 45 ns
—
— 50 ns
122
Tdtrf
Data out rise time and fall time PIC16F87/88
—
— 45 ns
PIC16LF87/88
—
— 50 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 18-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RB5/TX/CK
pin
RB2/RX/DT
pin
125
126
Note: Refer to Figure 18-3 for load conditions.
TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units Conditions
125
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time) 15
—
—
ns
126
TckL2dtl Data hold after CK↓ (DT hold time)
15
—
—
ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 187