PIC16F87 Datasheet, PDF(18/214 Page) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

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PIC16F87 Datasheet, PDF (18/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

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PIC16F87/88

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Details

page

Bank 2

100h(2) INDF

101h

102h(2)

103h(2)

104h(2)

TMR0

PCL

STATUS

FSR

105h WDTCON

106h PORTB

107h

108h

109h

10Ah(1,2) PCLATH

10Bh(2) INTCON

10Ch

10Dh

10Eh

10Fh

EEDATA

EEADR

EEDATH

EEADRH

Addressing this location uses contents of FSR to address data memory

(not a physical register)

Timer0 Module Register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

Indirect Data Memory Address Pointer

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

PORTB Data Latch when written; PORTB pins when read

Unimplemented

Write Buffer for the upper 5 bits of the Program Counter

GIE

PEIE

TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

EEPROM Data Register Low Byte

EEPROM Address Register Low Byte

â EEPROM Data Register High Byte

EEPROM Address Register High Byte

0000 0000

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

---0 1000

xxxx xxxx

---0 0000

0000 000x

xxxx xxxx

--xx xxxx

---- xxxx

26, 135

135

142

135

19, 69,

Bank 3

180h(2) INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

0000 0000 135

181h OPTION

RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 18, 69

182h(2) PCL

Program Counter (PC) Least Significant Byte

0000 0000 135

183h(2) STATUS

IRP

RP1

RP0

0001 1xxx 17

184h(2) FSR

Indirect Data Memory Address Pointer

xxxx xxxx 135

185h

Unimplemented

186h TRISB

PORTB Data Direction Register

1111 1111 58, 83

187h

Unimplemented

188h

Unimplemented

189h

Unimplemented

18Ah(1,2) PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 135

18Bh(2) INTCON

GIE

PEIE

TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF 0000 000x 19, 69,

18Ch EECON1

EEPGD

FREE

WRERR

WREN

x--x x000 28, 34

18Dh EECON2 EEPROM Control Register2 (not a physical register)

---- ---- 34

18Eh

Reserved, maintain clear

0000 0000 â

18Fh

Reserved, maintain clear

0000 0000 â

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose

contents are transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.

3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read â1â.

4: PIC16F88 device only.

DS30487B-page 16

Preliminary

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