PIC16F87 Datasheet, PDF (106/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
11.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the RB2/SDO/RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter, operating at x16 times
the baud rate; whereas, the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, RCIF (PIR1<5>), is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited, and no further data will be received. It is, therefore,
essential to clear error bit OERR if it is set. Framing
Error bit, FERR (RCSTA<2>), is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register, in
order not to lose the old FERR and RX9D information.
FIGURE 11-4:
USART RECEIVE BLOCK DIAGRAM
FOSC
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
CREN
÷64
or
÷16
OERR
FERR
MSb
RSR Register
LSb
STOP (8) 7 • • • 1 0 START
RB2/SDO/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
SPEN
Interrupt
RX9D RCREG Register
FIFO
RCIF
RCIE
8
Data Bus
FIGURE 11-5:
RX pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ASYNCHRONOUS RECEPTION
START
bit bit 0 bit 1
START
bit 7/8 STOP bit bit 0
bit
Word 1
RCREG
START
bit 7/8 STOP bit
bit
Word 2
RCREG
bit 7/8 STOP
bit
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS30487B-page 104
Preliminary
 2003 Microchip Technology Inc.