PIC16F87 Datasheet, PDF (118/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
The ADRESH:ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the A/D result register
pair, the GO/DONE bit (ADCON0<2>) is cleared, and
A/D Interrupt Flag bit, ADIF, is set. The block diagram
of the A/D module is shown in Figure 12-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 12.1. After this
sample time has elapsed, the A/D conversion can be
started.
These steps should be followed for doing an A/D
conversion:
1. Configure the A/D module:
• Configure analog/digital I/O (ANSEL)
• Configure voltage reference (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• SET PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 12-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
110
101
100
011
010
VIN
(Input Voltage)
001
A/D
Converter
VREF+
AVDD
000
(Reference
Voltage)
VCFG1:VCFG0
RB7/AN6/PGD/T1OSI
RB6/AN5/PGC/T1OSO/T1CKI
RA4/AN4/T0CKI/C2OUT
RA3/AN3/VREF+/C1OUT
RA2/AN2/CVREF/VREF-
RA1/AN1
RA0/AN0
VREF-
(Reference
Voltage)
AVSS
VCFG1:VCFG0
DS30487B-page 116
Preliminary
 2003 Microchip Technology Inc.