PIC16F87 Datasheet, PDF (51/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
TABLE 4-4: CLOCK SWITCHING MODES
Current
System
Clock
SCS bits <1:0>
Modified to:
Delay
OSTS IOFS T1RUN
bit bit bit
New
System
Clock
Comments
LP, XT, HS,
10
8 Clocks of 0
1⁽¹⁾
0
INTRC The internal RC oscillator
T1OSC,
(INTRC)
INTRC
or
frequency is dependant
EC, RC FOSC<2:0> = LP,
INTOSC upon the IRCF bits.
XT or HS
or
INTOSC
Postscaler
LP, XT, HS,
01
8 Clocks of 0
N/A
1
INTRC,
(T1OSC)
T1OSC
EC, RC FOSC<2:0> = LP,
XT or HS
T1OSC
T1OSCEN bit must be
enabled.
INTRC
00
8 Clocks of 1
N/A
0
EC
T1OSC FOSC<2:0> = EC
EC
or
or
or
RC
FOSC<2:0> = RC
RC
INTRC
00
1024 Clocks 1 N/A
0
LP, XT, HS During the 1024 clocks,
T1OSC FOSC<2:0> = LP, (OST)
program execution is
XT, HS
+
clocked from the second-
8 Clocks of
ary oscillator until the
LP, XT, HS
primary oscillator becomes
stable.
LP, XT, HS
00
1024 Clocks 1 N/A
0
LP, XT, HS When a RESET occurs,
(Due to RESET) (OST)
there is no clock transition
LP, XT, HS
sequence.
Instruction execution
and/or peripheral opera-
tion is suspended unless
Two-Speed Start-up mode
is enabled, after which the
INTRC will act as the
system clock until the OST
timer has expired.
Note 1: If the new clock source is INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms after the clock
change.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 49